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Advanced System-in-Package Design Services

Author: Date:6/27/2019 12:11:20 AM
    Integrating multiple different devices such as semiconductors and passive devices into a single package, or a miniaturized module, is called System-in-Package (SiP). Doing so can achieve a particularly fast and low-cost development cycle. This article will focus on the key benefits of developing SiP implementations specifically for RF applications, and how companies such as Insight SiP design services through Full-Turnkey and how to use their advanced packaging design methods to help customers succeed. of.

 

The integration of radio frequency systems using the SiP method has become the key to the miniaturization route. Although the integration of more and more features (system-on-a-chip concept) in a single die is a long-term trend, the never-ending growth in the complexity of small personal devices continues to push people to use SiP to implement a complete system. RF SiPs can be implemented using a variety of technologies, each of which has its own special aspects; therefore, SiP implementations need to be tailored to different materials, physical deposition methods and properties to suit specific design rules.

 

Regardless of which packaging/assembly technology is used, such as organic substrates (BT, FR4...), multilayer ceramic substrates (LTCC, HTCC, thick film...), wire bonding, flip chips, or thin films on silicon or glass Integrated Passive Components (IPD), etc., It is important that design company partners can combine their RF expertise with unique functional embedded capabilities within the package.

 

Why SiP methods can meet today's challenges

 

With the large-scale adoption of consumer electronics products incorporating increasingly complex functions, it is important that new devices meet the requirements of low power consumption and a smaller aspect ratio while maintaining strong price competitiveness. As a result, engineers and product development teams face multiple challenges, including the fact that reducing nodes no longer necessarily reduces the cost of each transistor (after 65 nm), SoC development time, non-recurring engineering costs (NRE), and failure risk The development of each generation of nodes continues to rise and high-growth markets (Internet of Things, cars...) require cost-effective integration of different functions in a small space (memory, MCU, GPU, analog, RF, MEMS, CIS...) .

 

Lower power consumption has replaced faster speeds as the most important IC requirement, and devices need to pass existing radio frequency protocols (such as cellular), or emerging networks (such as LoRa, SigFox, LTE-M, NB-IoT, etc. LPWAN ) to achieve wireless connection. Only the SiP method can help meet these typical requirements, because this system partitioning can provide the ability to surpass Moore's Law. SiP's modularity can simplify the implementation of adding different functions to digital SoCs. Packaging multiple dies in one IC package can reduce power consumption by 3 to 10 times compared to mounting multiple individually packaged dies on a printed circuit board.

 

Multi-die IC design and manufacturing processes are continuously maturing. They can reduce NRE and shorten development time, making SiP also have good economics for small and medium-sized batches. IDMs and fabless IC suppliers that have released many IC products based on intermediaries are now in production and are developing more such 2.5D-IC designs. Large open OEMs such as TSMC have also invested heavily in their own multi-die packaging lines, and most large OSAT companies have developed and delivered WLP solutions. In addition, several EDA vendors provide user-friendly modeling and design tools that can be used not only to minimize development time and risk, but also to reduce the price of multi-die ICs.